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INTEGRATED CIRCUITS
74F524 8-bit register comparator (open-collector + 3-State)
Product specification IC15 Data Handbook 1990 Aug 07
Philips Semiconductors
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
FEATURES
* 8-Bit bidirectional register with bus-oriented input-output * Independent serial input-output to register * Register bus comparator with `equal to', `greater than' and
`less than' outputs
PIN CONFIGURATION
S0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 1 2 3 4 5 6 7 8 9 10 20 VCC 19 S1 18 SE 17 C/SI 16 C/SO 15 EQ 14 GT 13 LT 12 M 11 CP
* Cascadable in groups of 8-bits * Open collector comparator outputs for AND-wired expansion * Two's complement or magnitude compare
DESCRIPTION
The 74F524 is an 8-bit bidirectional register with parallel input and output, plus serial input and output progressing from MSB to LSB. All data inputs, serial and parallel, are loaded by the rising edge of the clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-High, open collector outputs representing `register equal to bus', `register greater than bus' and `register less than bus' are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow Two's Complement as well as magnitude compare. Linking inputs are provided for expansion to longer words.
I/O7 GND
SF00970
TYPE 74F524
TYPICAL fMAX 65MHz
TYPICAL SUPPLY CURRENT (TOTAL) 110mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F524N N74F524D PKG DWG #
20-pin plastic DIP 20-pin plastic SOL
SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS I/On S0, S1 C/SI CP SE M I/On C/SO LT EQ Parallel data inputs Mode select inputs Status priority or serial data input Clock pulse input (active rising edge) Status enable input (active Low) Compare mode select input 3-state parallel data outputs Status priority or serial data output Register less than bus output Register equal to bus output DESCRIPTION 74F(U.L.) HIGH/LOW 3.5/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 50/33 OC/33 OC/33 OC/33 LOAD VALUE HIGH/LOW 70A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 3.0mA/24mA 1.0mA/20mA OC/20mA OC/20mA OC/20mA
GT Register greater than bus output NOTE: One (1.0) FAST Unit Load (U.L.) is defined as 20A in the High state and 0.6mA in the Low state. OC=Open Collector
1990 Aug 07
2
853-0373 00135
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
LOGIC SYMBOL for 74F456
12 18
SELECT FUNCTION TABLE
S0 L S1 L H L OPERATION HOLD-Retains data in shift register READ-Read contents in register onto data bus SHIFT-Allows serial shifting on next rising clock edge
M 17 1 19 11 C/SI S0 S1 CP
SE C/SO LT GT EQ 16 13 14 15
L H
H H LOAD-Load data on bus into register H = High voltage level L = Low voltage level One port of an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal register. Three active-OFF Open Collector outputs indicate whether the contents held in the shift register are `greater than' (GT). `less than' (LT), or `equal to' (EQ) the data on the input bus. A High signal on the Status Enable (SE) input disables these outputs to the OFF state. A mode control (M) input allows selection between a straightforward magnitude compare or a comparison between Two's complement numbers.
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
2 VCC = Pin 20 GND = Pin 10
3
4
5
6
7
8
9
SF00971
LOGIC SYMBOL (IEEE/IEC) for 74F456
COMP 1 19 11 12 17 18 2 3 4 5 6 7 8 9 0 1 M C4/2/4 M5 MAGNITUDE 2D M6 TWO's COMPLEMENT & G7 13 14 15 16 0 3 0=HOLD 1=READ 2=SHIFT 3=LOAD
NUMBER REPRESENTATION SELECT TABLE
M L Magnitude compare OPERATION
H Two's Complement compare H = High voltage level L = Low voltage level For `greater than' or `less than' detection, the C/SI input must be held High, as indicated in the Function Table. The internal logic is arranged such that a Low signal on the C/SI input places the `greater than' and `less than' outputs in their off state. (Note that this off state serves also as the active state when C/SI is High. It is intended for use in expansion to word lengths greater than 8 bits using multiple 74S524s as explained in the next 3 paragraphs.) The C/SO output will be forced High if the `equal to' status condition exists; otherwise, C/SO will be held Low. Word length expansion (in groups of 8 bits) can be achieved by connecting the C/SO output of the more significant byte to the C/SI input of the next less significant byte and also to its own SE input (see Application Figure 1). The CS/I input of the most significant device is held High while the SE input of the least significant device is held Low. The corresponding status outputs are AND-wired together. In the case of two's complement number compare, only the Mode input to the most significant device should be High. the Mode inputs to all other cascaded devices are held Low. Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, then the EQ and LT outputs will be pulled Low, whereas the GT output will float High. Also, the
3, 4D
1,5,6,7>I/O 1,5,6,7SF00972
FUNCTIONAL DESCRIPTION
The 74F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial loading. Parallel data may be read from or loaded into the registers via the data bus I/O0-I/O7. Serial data is loaded into the register from the C/SI input and may be shifted through the register and out through the C/SO output. Both parallel and serial data entry occurs on the rising edge of the clock (CP). The operation of the shift register is controlled by two signals, S0 and S1, according to the Select Function Table. The 3-State parallel output buffers are enabled only in the READ mode.
1990 Aug 07
3
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
CS/O output of the most significant device will be forced Low, disabling the subsequent devices but enabling its own status outputs. The corrected status condition is thus indicated. The same applies if the register byte is less than the data byte, only in this case the EQ and GT outputs go Low, whereas the LT output floats High. If an equality condition is detected in the most significant device, its C/SO output is forced High. This enables the next less significant
device and disables its own status outputs. In this way, the status output proximity is handed down to the next less significant device which now effectively becomes the most significant byte. The worst case propagation delay for a compare operation involving `n' cascaded 74F524s will be when an equality condition is detected in all but the least significant byte. In this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take 35+6(n-2) ns.
APPLICATION
VCC GREATER THAN EQUAL TO LESS THAN H = TWO's COMPLEMENT L = MAGNITUDE M H GT EQ LT SE C/SI C/SO S0 S1 I/O C/SI S0 S1 I/O C/SO C/SI S0 S1 I/O C/SO L M GT EQ LT SE M GT EQ LT SE L L
RD WR MSB 8 8 LSB 8
SF01012
Figure 1. Cascading 74F524s for Comparing Longer Words
FUNCTION TABLE
INPUTS SE H H H H H H H L L L L L L (1) = 2= H= L= X= C/SI H L X H L H L L L L H H S0 L L H L L H H H or L2 H or L2 H or L2 H or L2 H or L2 S1 L L L H H H H H or L2 H or L2 H or L2 H or L2 H or L2 Data comparison X X X X X X X OA-OH > I/O0-I/O7 OA-OH = I/O0-I/O7 OA-OH < I/O0-I/O7 OA-OH > I/O0-I/O7 OA-OH = I/O0-I/O7 EQ H H H H H H H L H L L H L OUTPUTS GT H H H H H H H H H H H L L LT H H H H H H H H H H L L H C/SO (1) L Q0 (1) L (1) L L L L L H L Compare (GT=CT=on) Compare (GT=CT=off) Load Shift Read OPERATING MODE
Hold
H H or L2 H or L2 OA-OH < I/O0-I/O7 High if I/On=Dn, otherwise Low Must meet setup and hold time requirements High voltage level Low voltage level Don't care
1990 Aug 07
4
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
LOGIC DIAGRAM
S0
1
S1 19 SE 18 17 C/SI
16
C/SO
15 CP Q I/O0 2 D Q
EQ
CP Q I/O1 3 D Q
CP Q I/O2 4 D Q
14
GT
CP Q I/O3 5 D Q
CP Q I/O4 6 D Q
CP Q I/O5 7 D Q
CP Q I/O6 8 D Q 13 LT
I/O7
9
CP Q D Q
CP 11 12 M
VCC = Pin 20 GND = Pin 10
SF00973
1990 Aug 07
5
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IO OUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state All except I/O Current applied to output in Low output state I/O only Operating free-air temperature range Storage temperature range 48 0 to +70 -65 to +150 mA C C PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +VCC 40 UNIT V V mA V mA
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK VOH IO OH Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output voltage High-level High level output current C/SO only All except I/O IO OL Tamb Low-level Low level output current I/O only Operating free-air temperature range 0 24 70 mA C -1 20 mA mA LT, EQ, GT only Not LT, EQ, GT, C/SO PARAMETER MIN 4.5 2.0 0.8 -18 4.5 -3 NOM 5.0 MAX 5.5 V V V mA V mA UNIT
1990 Aug 07
6
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL IOH PARAMETER High-level output current LT, EQ, GT only C/SO only VOH High-level output voltage I/On only TEST CONDITIONSNO TAG VCC = MIN, VIL = MAX, VIH = MIN, VOH = MAX VCC = MIN, MIN VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX MAX, VIH = MIN 10%VCC IOH=MAX 10%VCC 5%VCC 10%VCC IO = MAX OL 5%VCC 2.5 2.4 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 1 100 20 -0.6 70 -0.6 -60 110 -150 150 LIMITS MIN TYP2 MAX 250 UNIT A V V V V V V mA A A mA A mA mA mA
VO OL VIK II IIH IIL IOZH IOZL IOS ICC
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Except I/On Low-level input current Off-state output current High-level voltage applied I/On only Off-state output current Low-level voltage applied Short-circuit output current3 Supply current (total) Except LT, EQ, GT I/On Except I/On
VCC = MIN, II = IIK VCC = MAX, VI = 5.5V VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX VCC = MAX
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1990 Aug 07
7
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25C CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPLH tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL Maximum clock frequency Propagation delay I/On to EQ Propagation delay I/On to GT Propagation delay I/On to LT Propagation delay I/On to C/SO Propagation delay CP to EQ Propagation delay CP to GT Propagation delay CP to LT Propagation delay CP to C/SO (Load) Propagation delay CP to C/SO (Serial shift) Propagation delay C/SI to GT Propagation delay C/SI to LT Propagation delay Sn to C/SO Propagation delay SE to EQ Propagation delay SE to GT Propagation delay SE to LT Propagation delay C/SI to C/SO Propagation delay M to GT Propagation delay M to LT Output Enable time Sn to I/On Waveform 4 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 1 Waveform 1 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform NO TAG 50 9.0 4.5 8.5 6.5 8.0 6.0 7.0 6.5 11.0 4.0 11.0 10.0 11.0 8.0 10.0 5.0 4.5 8.0 3.0 8.0 3.0 6.5 5.5 3.5 2.5 6.0 3.5 5.0 3.5 4.0 4.0 8.0 8.0 10.0 6.0 4.5 5.5 TYP 65 11.5 7.5 11.0 9.5 11.0 10.5 13.0 9.0 17.0 8.0 16.0 16.5 16.0 14.0 16.0 10.0 9.0 10.5 4.5 10.5 6.0 8.0 10.0 7.0 4.5 8.0 5.0 8.0 5.5 7.0 7.0 13.0 10.0 15.0 8.0 7.0 9.0 17.0 11.0 17.0 15.5 17.0 14.0 16.0 14.0 22.0 14.0 20.0 21.0 23.0 18.0 20.0 13.0 11.5 16.0 8.5 17.0 8.5 14.5 17.0 10.5 8.0 13.0 8.0 12.0 8.0 11.0 11.0 18.0 15.5 20.0 12.0 13.0 15.0 MAX VCC = +5V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 45 9.0 4.5 8.5 6.5 8.0 6.0 7.0 5.5 10.0 4.0 10.0 10.0 10.0 8.0 10.0 5.0 4.5 9.0 2.5 8.0 2.5 6.5 5.5 3.5 2.5 6.0 3.0 5.0 3.0 4.0 4.0 8.0 8.0 10.0 5.0 4.5 5.5 18.0 12.0 18.0 16.5 18.0 15.0 17.0 15.0 23.0 15.0 21.0 22.0 24.0 19.0 21.0 14.0 12.5 17.0 9.5 18.0 9.5 15.5 18.0 11.5 9.0 14.0 9.0 13.0 9.0 12.0 12.0 19.0 16.5 21.0 13.0 14.0 16.0 MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
ns
tPHZ tPLZ
Output Disable time Sn to I/On
3.0 4.5
5.0 8.0
12.0 12.5
2.0 4.5
13.0 13.5
ns
1990 Aug 07
8
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low I/On to CP Hold time, High or Low I/On to CP Setup time, High or Low S0, S1 to CP Hold time, High or Low S0, S1 to CP Setup time, High or Low C/SI to CP Hold time, High or Low C/SI to CP CP pulse width, High or Low Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 4 6.0 6.0 0 0 13.5 10.0 0 0 7.0 7.0 0 0 5.0 10.0 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 6.0 6.0 0 0 15.0 10.0 0 0 7.0 7.0 0 0 5.0 10.0 MAX ns ns ns ns ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
C/SI
VM tPHL
VM tPLH VM VM
SE, C/SI, M I/On, Sn
VM tPHL
VM tPLH VM VM
GT, LT
EQ, C/SO GT, LT
SF00974
SF00975
Waveform 1. Propagation Delay for Inverting Outputs
Waveform 2. Propagation Delay for Non-Inverting Outputs
1/fMAX C/SI, I/On, Sn VM ts(H) VM VM th(H) VM ts(L) VM th(L) tPHL CP VM EQ, C/SO, GT, LT VM VM CP VM tW(H) tW(L) tPLH VM
SF00976
Waveform 3. Setup and Hold Times
SF00977
Waveform 4. Propagation Delay, Clock to Output, Clock Pulse Width, and Maximum Clock Frequency
1990 Aug 07
9
Philips Semiconductors
Product specification
8-bit register comparator (open collector + 3-State)
74F524
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
Sn VOH -0.3V I/On 0V VOL +0.3V VM tPZL VM VM tPLZ
Sn
VM tPZH
VM tPHZ VM
I/On
SF00978
SF00979
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs and Open Collector Outputs SWITCH POSITION TEST tPLZ, tPZL Open Collector All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00980
1990 Aug 07
10
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1990 Aug 07
11
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1990 Aug 07
12
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
NOTES
1990 Aug 07
13
Philips Semiconductors
Product specification
8-bit register comparator (open-collector + 3-State)
74F524
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05131
Philips Semiconductors
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